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// software and tools, and its AMPP partner logic functions, and any output 
// files from any of the foregoing (including device programming or simulation 
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module crc8(
	input			    iClk,      			//% Clock
	input               iRst,
	input			    iClr,				//% Clear CRC-8
    
	input			    iEn,				//% Clock enable
	input		[7:0]   ivByte,				//% Inbound byte
	
	output	reg	[7:0]   ovCrc8				//% Outbound CRC-8 byte
);

// Polynomial = x^8 + x^2 + x^1 + x^0
always @ ( posedge iClk or posedge iRst )
begin
	if (iRst)
		ovCrc8      <= 8'h00;
	else if ( iClr ) begin
		ovCrc8      <= 8'h00;
	end
	else begin
		if ( iEn ) begin   
				ovCrc8[0]       <= ivByte[7] ^ ivByte[6] ^ ivByte[0]
										^ ovCrc8[7] ^ ovCrc8[6] ^ ovCrc8[0];
				ovCrc8[1]       <= ivByte[6] ^ ivByte[1] ^ ivByte[0]
										^ ovCrc8[6] ^ ovCrc8[1] ^ ovCrc8[0];
				ovCrc8[2]       <= ivByte[6] ^ ivByte[2] ^ ivByte[1] ^ ivByte[0]
										^ ovCrc8[6] ^ ovCrc8[2] ^ ovCrc8[1] ^ ovCrc8[0];
				ovCrc8[3]       <= ivByte[7] ^ ivByte[3] ^ ivByte[2] ^ ivByte[1]
										^ ovCrc8[7] ^ ovCrc8[3] ^ ovCrc8[2] ^ ovCrc8[1];
				ovCrc8[4]       <= ivByte[4] ^ ivByte[3] ^ ivByte[2]
										^ ovCrc8[4] ^ ovCrc8[3] ^ ovCrc8[2];
				ovCrc8[5]       <= ivByte[5] ^ ivByte[4] ^ ivByte[3]
										^ ovCrc8[5] ^ ovCrc8[4] ^ ovCrc8[3];
				ovCrc8[6]       <= ivByte[6] ^ ivByte[5] ^ ivByte[4]
										^ ovCrc8[6] ^ ovCrc8[5] ^ ovCrc8[4];
				ovCrc8[7]       <= ivByte[7] ^ ivByte[6] ^ ivByte[5]
										^ ovCrc8[7] ^ ovCrc8[6] ^ ovCrc8[5];
		end
	end
end

endmodule
